In manufacturing semiconductor devices, it is imperative that the devices are free of defects at the time of production, and reliable throughout their use. When defects are found in completed devices, the percentage of usable devices decreases, and the profitability of the manufacturer suffers. More importantly, when a semiconductor device fails after it has been installed in a device, such a failure may cause the entire device to fail. That is, the failure of a single semiconductor device may render an entire consumer electronics device unusable. Accordingly, it is important that manufacturers of semiconductor devices minimize defects whenever possible.
One area where defects may occur is in the area of wire bonding. Wire bonds are used to connect a bond pad on one element of a device, such as a die, to a bond pad on another element, such as a substrate receiving the die. While integrated circuits may be manufactured using flip chip technology where balls on the bottom of the die are directly connected to contact pads on a substrate, integrated circuits manufactured using wire bonding is generally cheaper than integrated circuits using flip chip technology. Stress generated during the bonding process and stress from material contacting the bonded structures during assembly of the integrated circuit package tend to propagate to substructures under the bond pad. The stress may cause failure of the interconnects, and in some cases, may cause the substructure to fail through cracks.
One type of device which may implement wire bonds is a programmable logic device (PLD). A PLD is designed to be user-programmable so that users may implement logic designs of their choices. Since their introduction, the capabilities of PLDs have rapidly improved. The combination of rich feature sets with device programmability and re-programmability has made PLDs highly adaptive to design changes during and after product development and, consequently, useful in a large variety of applications. However, because of the possibility of defects resulting from the attachment of wire bonds to contact pads, active devices and interconnects are often not positioned in the areas under the contact pads in conventional circuits to avoid damage to active devices, and in particular, metal oxide semiconductor (MOS) devices. While active devices such as junction diodes or bipolar transistors which do not have a dielectric layer and a gate may be formed on the edge of the substrate, other active devices such as metal oxide semiconductor (MOS) devices are often not formed along the edge of the device. MOS devices may include, for example, metal oxide semiconductor field effect (MOSFET) transistors having a gate formed over a dielectric layer formed on the diffusion regions. That is, MOS devices comprise a dielectric layer over the substrate which, along with other elements such as a gate of a MOSFET, may be damaged during wire bonding. While structures may be provided which may protect the MOS structures below the contact pad, such structures fail to provide additional functionality, but rather inhibit interconnect paths and occupy area within the metal layers.
Accordingly, there is a need for an improved integrated circuit and method of implementing a contact pad on an integrated circuit.